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IEEE International Workshop on Hardware-Oriented Security and Trust
(HOST 2010)

June 13-14, 2010
Anaheim Convention Center, Anaheim, CA

http://www.engr.uconn.edu/HOST

Co-located with DAC 2010
The 47th Design Automation Conference

CALL FOR PARTICIPATION

Scope -- Advance Program -- More Information -- Committees

Scope

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The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust (HOST) issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g., to act as a 'kill switch' to disable a chip, to integrated circuit (IC) piracy, and to attacks designed to extract encryption keys and IP from a chip. HOST covers security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems. The mission of HOST is to provide a forum for the presentation and discussion of research that is of critical significance to the security of, and trust in, modern society's microelectronic-supported infrastructures.

Advance Program
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Sunday -- Monday

June 13, 2010 (Sunday)
 
8:40 AM - 10:20 AM OPENING SESSION
8:40 - 9:00
Opening Remarks
9:00 - 10:20

Plenary Session
Jim Adams (TAEUS)
Randy Torrance (ChipWorks)

 
10:20 AM - 10:40 AM BREAK
 
10:40 AM - 11:40 AM Session 1 - ATTACKS
  Entropy-based Power Attack
H. Maghrebi, S. Guilley, J-L Danger and F. Flament
 

Low Voltage Fault Attacks to AES
A. Barenghi, G. Bertoni. L. Breveglieri, M. Pellicioli and G. Pelosi

 

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach
S. Narasimhan, R. Chakraborty, D. Du, S. Paul, F. Wolff, C. Papachristou and S. Bhunia

 
11:40 AM - 1:00 PM LUNCH
 
1:00 PM - 2:20 PM Session 2 - INDUSTRIAL
 

Invited Talk
Pankaj Rohatgi (CRI)

  Anti-tamper JTAG TAP design enables DRM to JTAG registers and P1687 on-chip instruments
CJ Clark
  Using Multiple Processors In a Single Reconfigurable Fabric for High-Assurance Applications
B. Newgard and C. Hoffman
  
 
2:20 PM - 2:40 PM BREAK
 
2:40 PM - 3:40 PM Session 3 - ELLIPTIC CURVE CRYPTOGRAPHY
  State-of-the-art of secure ECC implementations: a survey on known side-channel attacks and countermeasures
J. Fan, X. Guo, E. De Mulder, P. Schaumont, B. Preneel and I. Verbauwhede
  
  Efficient One-Pass Entity Authentication Protocol based on ECC for Constrained Devices
J. Heyszl and F. Stumpf
 
3:40 PM - 4:00 PM BREAK
 
4:00 PM - 5:00 PM Session 4 - WATERMARKING
  Side-Channel Based Watermarks for Integrated Circuits
G. Becker, M. Kasper, A. Moradi and C. Paar
  
  Multiplexing Methods for Power Watermarking
D. Ziener, F. Baueregger and J. Teich
  Provably Secure Diverse Watermarks for Sequential Circuits
Y. Alkabani and F. Koushanfar
 
5:00 PM - 5:20 PM BREAK
 
5:20 PM - 6:00 PM Poster Session
 
7:00 PM - 9:00 PM WINE AND CHEESE RECEPTION
 
June 14, 2010 (Monday)
 
9:20 AM - 10:00 AM Monday KEYNOTE
Christof Paar (University of Bochum)
 
10:00 AM - 10:20 AM BREAK
 
10:20 AM - 11:40 AM Session 5 - PHYSICAL UNCLONABLE FUNCTIONS
  A Large Scale Characterization of RO-PUF
A. Maiti and P. Schaumont
  
  LISA: Maximizing RO PUF's Secret Extraction
C. Yin and G. Qu
  Attack Resistant Sense Amplifier Based PUFs (SA-PUF) with Deterministic and Controllable Reliability of PUF Responses
M. Bhargava, C. Cakir and K. Mai
  Sensor Physical Unclonable Functions
K. Rosenfeld, E. Gavas and R. Karri
  
 
11:40 AM - 1:00 PM LUNCH
 
1:00 PM - 2:20 PM Panel: EVALUATING TROJAN DETECTION SCHEMES
 
2:20 PM - 2:40 PM BREAK
 
2:40 PM - 4:00 PM Session 6 - IMPLEMENTATIONS AND COUNTERMEASURES
  Current Flattening Circuit for DPA Countermeasure
E. Laohavaleeson and C. Patel
  
  Side-Channel Attack Resistant ROM-Based AES S-Box
C. Teegarden, M. Bhargava, and K. Mai
  Hardware Implementation of Hash Function Luffa
A. Satoh, T. Katashita, T. Sugawar, T. Aoki and N. Homma
  
  Entropy Extraction in Metastability-based TRNG
V. Suresh and W. Burleson
  
 
4:00 PM - 4:20 PM BREAK
 
4:20 PM - 5:20 PM Panel: What should academics be researching? What should be left to industry?
 
5:20 PM - 5:40 PM CLOSING REMARKS
 
Note: This is a preliminary agenda. Talk days, times, and ordering subject to change.
More Information
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General Information

GENERAL CHAIR
Jim Plusquellic
Electrical and Computer Engineering Department
University of New Mexico
Tel: (505) 277-0785, x-1439
E-mail: jimp@ece.unm.edu

Program Information

PROGRAM CHAIR
Ken Mai
Electrical and Computer Engineering Department
Carnegie Mellon University
Tel: (412) 268-8335, x-1374
E-mail: kenmai@ece.cmu.edu

Committees
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GENERAL CHAIR
Jim Plusquellic
Univ. of New Mexico

PROGRAM CHAIR
Ken Mai
Carnegie Mellon Univ.

VICE-PROGRAM CHAIR
Patrick Schaumont
Virginia Tech

PAST CHAIR
Mohammad Tehranipoor
Univ. of Connecticut

PUBLICITY CHAIR
Ted Huffmire
Naval Postgrad School

PUBLICATION CHAIR
Ramesh Karri
Polytechnic University

FINANCE CHAIR
Michael Hsiao
Virginia Tech

EUROPEAN LIAISON
Ingrid Verbauwhede
K.U.Leuven

ASIAN LIAISON
Akashi Satoh, RCIS
AIST

INDUSTRIAL LIAISON
Farinaz Koushanfar
Rice Univ

STEERING COMMITTEE
Mohammad Tehranipoor, UConn (Chair)
Jim Plusquellic, UNM
Farinaz Koushanfar, Rice University
Miodrag Potkonjak, UCLA

PROGRAM COMMITTEE
Miron Abramovici, DAFCA
Dhruva Acharyya, Verigy
Divya Arora, Intel
Swarup Bhunia, Case Western U.
C.J. Clark, Intellitech Corp.
Jennifer Dworak, Brown University
Saverio Fazzari, BAH
Yunsi Fei, U. of Connecticut
Sylvain Guilley, Telecom-paristech
Ian Harris, UC Irvine
Michael Hsiao, Virginia Tech
Ted Huffmire, NPS
David Hwang, George Mason Univ.
Niraj Jha, Princeton
Ramesh Karri, Polytechnic NY
Ryan Kastner, UC San Diego
Tom Kean, Algotronix Consult, UK
Farinaz Koushanfar, Rice University
John Lach, U. of Virginia
Yiorgos Makris, Yale University
Christof Paar, U. of Bochum
Pascal Paillier, Gemalto
Chris Papachristou, Case Western
Bart Preneel, Katholieke U. Leuven
Gang Qu, U. of Maryland
Anand Raghunathan, Purdue Univ.
Matthieu Rivain, Cryptoexperts
Pankaj Rohtagi, IBM
Ahmad Sadeghi, U. of Bochum
Patrick Schaumont, Virginia Tech
S. Skorobogatov, U. Cambridge
Mani Soma, U. of Washington
Berk Sunar, WPI
Steve Trimberger, Xilinx
Pim Tuyls, Intrinsic-ID
Ingrid Verbauwhede, K.U.Leuven
Daniel Weyer, Rockwell
Francois Xavier Standaert, UCL

For more information, visit us on the web at: http://www.engr.uconn.edu/HOST

The IEEE International Workshop on Hardware-Oriented Security and Trust (HOST 2010) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).


IEEE Computer Society- Test Technology Technical Council

TTTC CHAIR
Adit D. SINGH
Auburn University - USA
Tel. +1-334-844-1847
E-mail adsingh@eng.auburn.edu

PAST CHAIR
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

TTTC 1ST VICE CHAIR
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

SECRETARY
Christian LANDRAULT
LIRMM - France
Tel. +33-4-674-18524
E-mail landrault@lirmm.fr

ITC GENERAL CHAIR
Gordon W. ROBERTS
McGill University
- Canada
Tel. +1-514-398-6029
E-mail gordon.roberts@mcgill.ca

TEST WEEK COORDINATOR
Yervant ZORIAN
Virage Logic Corporation - USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

TUTORIALS AND EDUCATION
Dimitris GIZOPOULOS

University of Piraeus
- Greece
Tel. +30-210-414-2372
E-mail dgizop@unipi.gr

STANDARDS
Rohit KAPUR

Synopsys
, Inc. - USA
Tel. +1-650-934-1487
E-mail rkapur@synopsys.com

EUROPE
Zebo PENG
Linköping University - Sweden
Tel. +46-13-282-067/-281-000
E-mail zpe@ida.liu.se

MIDDLE EAST & AFRICA
Ibrahim HAJJ
American University of Beirut - Lebanon
Tel. +961-1-341-952
E-mail ihajj@aub.edu.lb

STANDING COMMITTEES
André IVANOV
University of British Columbia - Canada
Tel. +1-604-822-6936
E-mail ivanov@ece.ubc.ca

ELECTRONIC MEDIA
Alfredo BENSO
Politecnico di Torino - Italy
Tel. +39-011-564-7080
E-mail alfredo.benso@polito.it

 

PRESIDENT OF BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com

SENIOR PAST CHAIR
Paolo PRINETTO
Politecnico di Torino - Italy
Tel. +39-011-564-7007
E-mail Paolo.Prinetto@polito.it

TTTC 2ND VICE CHAIR
Chen-Huan CHIANG

Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

FINANCE
Michael NICOLAIDIS
TIMA Laboratory - France
Tel. +33-4-765-74696
E-mail michael.nicolaidis@imag.fr

IEEE DESIGN & TEST EIC
K.T. (Tim) CHENG
University of California, Santa Barbara - USA
Tel. +1-805-893-72942
E-mail timcheng@ece.ucsb.edu

TECHNICAL MEETINGS
Chen-Huan CHIANG
Alcatel-Lucent
- USA
Tel. +1-973-386-6759
E-mail chenhuan@alcatel-lucent.com

TECHNICAL ACTIVITIES
Matteo SONZA REORDA
Politecnico di Torino - Italy
Tel.+39-011-564-7055
E-mail matteo.sonzareorda@polito.it

ASIA & PACIFIC
Kazumi HATAYAMA
STARC - Japan
Tel. +
E-mail hatayama.kazumi@starc.or.jp

LATIN AMERICA
Victor Hugo CHAMPAC
Instituto Nacional de Astrofisica - Mexico
Tel.+52-22-470-517
E-mail champac@inaoep.mx

NORTH AMERICA
William R. MANN
SW Test Workshop - USA
Tel. +1-949-645-3294
E-mail william.mann@ieee.org

COMMUNICATIONS
Cecilia METRA
Università di Bologna - Italy
Tel. +39-051-209-3038
E-mail cmetra@deis.unibo.it

INDUSTRY ADVISORY BOARD
Yervant ZORIAN
Virage Logic Corporation- USA
Tel. +1-510-360-8035
E-mail yervant.zorian@viragelogic.com


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